As integrated circuit complexity increases, meeting the testing requirements for acceptable quality assurance is becoming increasingly difficult. Automated testing involves applying test signals to each manufactured circuit in various patterns designed to detect defects that cause improper circuit behavior. Although most modern integrated circuits comprise a number of interconnected cells selected from a library, early testing schemes assumed that faults occurred only between cell instances, at the cell I/O ports, or elsewhere outside cells altogether. The test patterns generated therefore did not necessarily include those needed to detect circuit faults inside a cell.
A more recently developed methodology for ATPG is termed “cell-aware”. This approach directly targets defects inside a given library cell, typically those defects that have been extracted from the actual circuit design layout. Such defects may be physically correlated to actual observed fabrication errors, and are therefore of particular interest. Bridge defects causing an unintended short or low-resistance connection, and open defects causing an unintended disconnection, for example are typically of highest interest. Defect prediction tools are commercially available to estimate defect probabilities for given circuit structures, such as long narrow closely-spaced parallel metal runs, etc. Some integrated circuit manufacturers may provide additional information of use in estimating the occurrence of defects.
FIG. 1 shows an exemplary conventional cell-aware ATPG flow that has been implemented with commercially available design tools. The flow starts with layout extraction 104, which produces a transistor netlist 106 and a list of possible faults or defects of interest 108, from the cell layout 102. Next, for each extracted defect, a transistor-level analog (e.g., SPICE) simulation 110 determines the complete set of cell input combinations that detect the defect by recognizing the resulting incorrect circuit behavior.
A cell-aware synthesis 114 process optimizes a defect detection matrix 112 resulting from fault model evaluation, to generate the corresponding library view 116 and simplify the subsequent ATPG. The library view contains one or more alternative conditions for detecting the corresponding defect for each cell-internal defect in the fault list. The final ATPG step 118 generates test patterns from the library view 116 that provide a higher percentage of defect detection or “test coverage” 120 compared to test patterns generated via other fault models. Cell-aware ATPG flows have achieved compelling results and are thus becoming increasingly popular.
However, the cell-aware fault model creation process relies on exhaustive analog simulation 110 to determine if a particular defect is detectable, from the severity of improper circuit behavior it causes. Each cell is first simulated without defects to determine the proper cell output voltages for every cell input combination. The analog simulator then inserts or injects a defect selected from the defects of interest into the circuit schematic by modifying the transistor-level netlist or component values. For example, if a fault is a bridge, then a small resistor is inserted between the corresponding nodes. For an open fault, the affected electrical components are disconnected (or a very high resistance is inserted).
A set of digital input patterns is simulated on the modified netlist, and the results are analyzed. If the analog simulator determines that a given defect is detectable, the simulator further determines the detection conditions for detecting that defect. That is, it notes those input patterns that elicit sufficiently severe improper circuit behavior, for concise test pattern generation. The analog simulator may therefore need to perform a very large number of analog simulations for every library cell to simulate a large number of defects.
In one exemplary processor design, early prior art methods generated 17,000 test patterns, and the cell-aware ATPG method generated an additional 7,000 test patterns. For a single library cell in this example, transistor-level analog simulations were run for each of forty-eight faults in the extracted fault list, for a total of forty-nine simulations per fault including the fault-free case. The fault count for an entire cell library, often having up to 1800 cells, is expected to scale accordingly, so characterizing a library may require nearly 100,000 individual analog fault simulations. While some fault simulations may require only DC solutions, others may require more time-consuming at-speed transient results.
Even with today's computer hardware and commercially available analog simulators, cell-aware ATPG simulations may require days of run time for a complete cell library characterization. This simulation bottleneck severity is likely to worsen as circuit density and complexity grows, causing more potential intra-cell fault locations in standard cell libraries. Accordingly, the inventors have developed a more efficient analog simulation solution to support cell-aware automated test pattern generation by using simulation techniques for fault sensitivity analysis.